1. Field of the Invention
The subject invention relates to image sensor circuitry, and more particularly, to a buffered direct injection pixel circuit for an infra-red focal plane array, having the characteristics of reduced size, low noise and low power consumption.
2. Background of the Related Art
Infrared detector systems typically require sophisticated tracking algorithms to accommodate the large and often dynamic changes in background information that results from the relatively high contrast and solar content of the radiation. Detectors operating in the infrared (IR) spectral band, however, can attain the same or greater thermal sensitivity with reduced signal processing complexity. As a result, infrared detection and tracking can often be accomplished using smaller, more cost-effective sensors having IR focal plane arrays (FPAs).
Unfortunately, IR focal plane arrays and multiplexing readout circuits have design constraints that can severely limit system performance. In the readout portion of an FPA, for example, the input amplifier cell circuitry that couples each photo detector to the corresponding readout site must perform several functions that are difficult to incorporate simultaneously in the small amount of space or “real estate” that is typically available on a signal processing chip.
A detector/amplifier cell of an FPA should ideally include: a detector interface stage that provides low impedance at a uniform operating bias; a large charge handling integration capacitance; a stage for uniform suppression of the background if integration capacity is inadequate; low power pixel multiplexing and reset stages; and an output stage adequate to drive the bus line capacitance for subsequent multiplexing at video rates.
Prior art IR FPAs typically lack impedance buffering, which forces a variation in detector dark currents and an increase in fixed pattern noise (i.e., spatial noise remaining after application of conventional two-point non-uniformity correction). Fixed pattern noise creates a visible mask in the imagery that obscures low contrast, high frequency information, thus degrading the minimum resolvable temperature and compromising performance under adverse conditions. Moreover, prior art devices lack capability for reducing pixel pitch and increasing pixel density. If the pixel pitch and detector/amplifier cell real estate are reduced in prior art devices, the performance limitations are further aggravated. When pixel pitch continues to decrease, issues of power and noise are become even more formidable.
Given the current state-of-the-art and the limited chip area available, there is insufficient detector/amplifier cell real estate for a readout circuit with conventional architecture to integrate all of the most important features such as low input impedance, uniform detector bias, and satisfactory charge storage capacity. However, because small cells are necessary for FPAs with high pixel counts, integrated readout circuits with reasonable die sizes, and compact optics, all the important functions of the readout circuit must be integrated in as little cell real estate as possible. Thus, there is a need for a pixel readout circuit with improved architecture having characteristics that are better optimized for use in an IR FPA.